Fetch-Decode-Execute Cycle

What is Fetch-Decode-Execute Cycle?

The repeating three-stage process by which a CPU runs a program: the next instruction is fetched from memory into the CPU using the program counter, memory address register, address bus, control bus, data bus, memory data register and current instruction register; the control unit then decodes it; and finally the control unit issues the signals that execute it, using the ALU and accumulator where an operation is required.

This definition is part of the Hardware chapter in Cambridge O Level Computer Science.

Concepts related to Fetch-Decode-Execute Cycle

• Control Unit
• Program Counter
• buses
• clock